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Freescale Semiconductor /MKL04Z4 /NVIC /NVIC_ICER

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Interpret as NVIC_ICER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)CLRENA0 0 (0)CLRENA1 0 (0)CLRENA2 0 (0)CLRENA3 0 (0)CLRENA4 0 (0)CLRENA5 0 (0)CLRENA6 0 (0)CLRENA7 0 (0)CLRENA8 0 (0)CLRENA9 0 (0)CLRENA10 0 (0)CLRENA11 0 (0)CLRENA12 0 (0)CLRENA13 0 (0)CLRENA14 0 (0)CLRENA15 0 (0)CLRENA16 0 (0)CLRENA17 0 (0)CLRENA18 0 (0)CLRENA19 0 (0)CLRENA20 0 (0)CLRENA21 0 (0)CLRENA22 0 (0)CLRENA23 0 (0)CLRENA24 0 (0)CLRENA25 0 (0)CLRENA26 0 (0)CLRENA27 0 (0)CLRENA28 0 (0)CLRENA29 0 (0)CLRENA30 0 (0)CLRENA31

CLRENA7=0, CLRENA25=0, CLRENA17=0, CLRENA10=0, CLRENA26=0, CLRENA12=0, CLRENA8=0, CLRENA5=0, CLRENA19=0, CLRENA23=0, CLRENA4=0, CLRENA30=0, CLRENA28=0, CLRENA21=0, CLRENA13=0, CLRENA29=0, CLRENA24=0, CLRENA18=0, CLRENA1=0, CLRENA27=0, CLRENA22=0, CLRENA14=0, CLRENA15=0, CLRENA9=0, CLRENA2=0, CLRENA0=0, CLRENA3=0, CLRENA6=0, CLRENA11=0, CLRENA20=0, CLRENA31=0, CLRENA16=0

Description

Interrupt Clear Enable Register

Fields

CLRENA0

no description available

0 (0): write: no effect; read: DMA channel 0 transfer complete interrupt disabled

1 (1): write: disable DMA channel 0 transfer complete interrupt; read: DMA channel 0 transfer complete interrupt enabled
CLRENA1

no description available

0 (0): write: no effect; read: DMA channel 1 transfer complete interrupt disabled

1 (1): write: disable DMA channel 1 transfer complete interrupt; read: DMA channel 1 transfer complete interrupt enabled
CLRENA2

no description available

0 (0): write: no effect; read: DMA channel 2 transfer complete interrupt disabled

1 (1): write: disable DMA channel 2 transfer complete interrupt; read: DMA channel 2 transfer complete interrupt enabled
CLRENA3

no description available

0 (0): write: no effect; read: DMA channel 3 transfer complete interrupt disabled

1 (1): write: disable DMA channel 3 transfer complete interrupt; read: DMA channel 3 transfer complete interrupt enabled
CLRENA4

no description available

0 (0): write: no effect; read: Reserved iv 20 interrupt disabled

1 (1): write: disable Reserved iv 20 interrupt; read: Reserved iv 20 interrupt enabled
CLRENA5

no description available

0 (0): write: no effect; read: Command complete and read collision interrupt disabled

1 (1): write: disable Command complete and read collision interrupt; read: Command complete and read collision interrupt enabled
CLRENA6

no description available

0 (0): write: no effect; read: Low-voltage detect, low-voltage warning interrupt disabled

1 (1): write: disable Low-voltage detect, low-voltage warning interrupt; read: Low-voltage detect, low-voltage warning interrupt enabled
CLRENA7

no description available

0 (0): write: no effect; read: Low Leakage Wakeup interrupt disabled

1 (1): write: disable Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt enabled
CLRENA8

no description available

0 (0): write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled

1 (1): write: disable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled
CLRENA9

no description available

0 (0): write: no effect; read: Reserved iv 25 interrupt disabled

1 (1): write: disable Reserved iv 25 interrupt; read: Reserved iv 25 interrupt enabled
CLRENA10

no description available

0 (0): write: no effect; read: Serial Peripheral Interface 0 interrupt disabled

1 (1): write: disable Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt enabled
CLRENA11

no description available

0 (0): write: no effect; read: Reserved iv 27 interrupt disabled

1 (1): write: disable Reserved iv 27 interrupt; read: Reserved iv 27 interrupt enabled
CLRENA12

no description available

0 (0): write: no effect; read: UART0 status and error interrupt disabled

1 (1): write: disable UART0 status and error interrupt; read: UART0 status and error interrupt enabled
CLRENA13

no description available

0 (0): write: no effect; read: Reserved iv 29 interrupt disabled

1 (1): write: disable Reserved iv 29 interrupt; read: Reserved iv 29 interrupt enabled
CLRENA14

no description available

0 (0): write: no effect; read: Reserved iv 30 interrupt disabled

1 (1): write: disable Reserved iv 30 interrupt; read: Reserved iv 30 interrupt enabled
CLRENA15

no description available

0 (0): write: no effect; read: Analog-to-Digital Converter 0 interrupt disabled

1 (1): write: disable Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt enabled
CLRENA16

no description available

0 (0): write: no effect; read: Comparator 0 interrupt disabled

1 (1): write: disable Comparator 0 interrupt; read: Comparator 0 interrupt enabled
CLRENA17

no description available

0 (0): write: no effect; read: Timer/PWM module 0 interrupt disabled

1 (1): write: disable Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt enabled
CLRENA18

no description available

0 (0): write: no effect; read: Timer/PWM module 1 interrupt disabled

1 (1): write: disable Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt enabled
CLRENA19

no description available

0 (0): write: no effect; read: Reserved iv 35 interrupt disabled

1 (1): write: disable Reserved iv 35 interrupt; read: Reserved iv 35 interrupt enabled
CLRENA20

no description available

0 (0): write: no effect; read: Real-time counter interrupt disabled

1 (1): write: disable Real-time counter interrupt; read: Real-time counter interrupt enabled
CLRENA21

no description available

0 (0): write: no effect; read: RTC seconds interrupt disabled

1 (1): write: disable RTC seconds interrupt; read: RTC seconds interrupt enabled
CLRENA22

no description available

0 (0): write: no effect; read: Periodic Interrupt Timer interrupt disabled

1 (1): write: disable Periodic Interrupt Timer interrupt; read: Periodic Interrupt Timer interrupt enabled
CLRENA23

no description available

0 (0): write: no effect; read: Reserved iv 39 interrupt disabled

1 (1): write: disable Reserved iv 39 interrupt; read: Reserved iv 39 interrupt enabled
CLRENA24

no description available

0 (0): write: no effect; read: Reserved iv 40 interrupt disabled

1 (1): write: disable Reserved iv 40 interrupt; read: Reserved iv 40 interrupt enabled
CLRENA25

no description available

0 (0): write: no effect; read: Reserved iv 41 interrupt disabled

1 (1): write: disable Reserved iv 41 interrupt; read: Reserved iv 41 interrupt enabled
CLRENA26

no description available

0 (0): write: no effect; read: Reserved iv 42 interrupt disabled

1 (1): write: disable Reserved iv 42 interrupt; read: Reserved iv 42 interrupt enabled
CLRENA27

no description available

0 (0): write: no effect; read: Multipurpose Clock Generator interrupt disabled

1 (1): write: disable Multipurpose Clock Generator interrupt; read: Multipurpose Clock Generator interrupt enabled
CLRENA28

no description available

0 (0): write: no effect; read: Low-Power Timer interrupt disabled

1 (1): write: disable Low-Power Timer interrupt; read: Low-Power Timer interrupt enabled
CLRENA29

no description available

0 (0): write: no effect; read: Reserved iv 45 interrupt disabled

1 (1): write: disable Reserved iv 45 interrupt; read: Reserved iv 45 interrupt enabled
CLRENA30

no description available

0 (0): write: no effect; read: PORTA Pin detect interrupt disabled

1 (1): write: disable PORTA Pin detect interrupt; read: PORTA Pin detect interrupt enabled
CLRENA31

no description available

0 (0): write: no effect; read: PORTB Pin detect interrupt disabled

1 (1): write: disable PORTB Pin detect interrupt; read: PORTB Pin detect interrupt enabled

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data